1. Field of the Invention
The present invention relates generally to microelectronic fabrications having formed therein terminal electrode structures. More particularly, the present invention relates to microelectronic fabrications having formed therein terminal electrode structures which provide enhanced barrier properties.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
In conjunction with various means and configurations for interconnecting microelectronic fabrications of various varieties, it is common in the art of microelectronic fabrication to employ integral to individual microelectronic fabrications terminal electrode structures at locations within the individual microelectronic fabrications where the individual microelectronic fabrications are to be interconnected. Such terminal electrode structures are typically formed integral to the individual microelectronic fabrications while employing various metallurgy layers, which under certain circumstances may include solder interconnection layers, to which the various means and configurations for interconnecting the microelectronic fabrications may be connected.
While terminal electrode structures are thus desirable and clearly essential within the art of microelectronic fabrication for effectively providing electrical interconnections for various varieties of microelectronic fabrications which may be fabricated within the art of microelectronic fabrication, terminal electrode structures are nonetheless not entirely without problems in the art of microelectronic fabrication when fabricating microelectronic fabrications. In that regard, it is typically highly desirable within the art of microelectronic fabrication, but nonetheless not always readily achievable within the art of microelectronic fabrication, to provide within a microelectronic fabrication a terminal electrode structure which provides enhanced barrier properties within the microelectronic fabrication within which is formed the terminal electrode structure.
It is thus towards the goal of providing for use when fabricating a microelectronic fabrication a terminal electrode structure which provides enhanced barrier properties within the microelectronic fabrication within which is formed the terminal electrode structure that the present invention is directed.
Various configurations and materials have been disclosed within the art of microelectronic fabrication for fabricating, with desirable properties, electrode structures within microelectronic fabrications.
For example, Agarwala et al., in U.S. Pat. No. 5,130,779, disclose: (1) a multi-layer solder layer terminal electrode structure with an enhanced aspect ratio for use within a microelectronic fabrication for directly interconnecting, with attenuated physical stress and strain, a pair of microelectronic substrates within the microelectronic fabrication; and (2) a method for forming the multi-layer solder layer terminal electrode structure with the enhanced aspect ratio for use within the microelectronic fabrication for directly interconnecting, with attenuated physical stress and strain, the pair of microelectronic substrates within the microelectronic fabrication. To realize the foregoing objects, the method for forming the multi-layer solder layer terminal electrode structure employs forming upon at least one terminal electrode solder layer employed within the multi-layer solder layer terminal electrode structure, prior to thermal reflow of the at least one terminal electrode solder layer: (1) a capping or encapsulant metal layer, or in the alternative; (2) a sidewall spacer layer, such that upon thermal reflow of the at least one terminal electrode solder layer the at least one terminal electrode solder layer is not susceptible to thermal reflow induced collapse.
In addition, Gaul, in U.S. Pat. No. 5,682,062, discloses a microelectronic fabrication system for interconnecting, with high areal density, integrated circuit die which are employed for fabricating the microelectronic fabrication system. To effect the foregoing result, the integrated circuit die employed within the microelectronic fabrication system may be fabricated in a fashion such that there is formed within the integrated circuit die a via an end portion of which is fashioned in the shape of either a prong or a receptacle, such that the integrated circuit die may be stacked to provide the microelectronic fabrication having fabricated therein the integrated circuit die with high areal density.
Finally, Hong, in U.S. Pat. No. 5,920,794, discloses an electrode structure which may be employed for making contact to a silicon semiconductor substrate within a semiconductor integrated circuit microelectronic fabrication while providing enhanced electromigration resistance within the semiconductor integrated circuit microelectronic fabrication within which is formed the electrode structure. The electrode structure which provides the enhanced electromigration resistance within the semiconductor integrated circuit microelectronic fabrication within which is formed the electrode structure comprises a multi-layer stack which in turn comprises, in the alterative: (1) a PtSi/TiW/TiW(N)/Au multi-layer stack; or (2) a PtSi/TiW/TiW(N)/TiW/Au multi-layer stack.
Desirable for use when fabricating microelectronic fabrications are additional terminal electrode structures which provide enhanced barrier properties within a microelectronic fabrication within which is formed the terminal electrode structure.
It is towards the foregoing object that the present invention is directed.